View FS7145_639267.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
1.0 Features
* Extremely flexible and low-jitter phase-locked loop (PLL) frequency synthesis * No external loop filter components needed * 150MHz CMOS or 340MHz PECL outputs * Completely configurable via I2CTM-bus * Up to four FS7140 or FS7145 can be used on a single I2C-bus * 3.3V operation * Independent on-chip crystal oscillator and external reference input * Very low "cumulative" jitter
Data Sheet
2.0 Description
The FS7140 / FS7145 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of electronic systems. Via the I2Cbus interface, the FS714x can be adapted to many clock generation requirements. The length of the reference and feedback dividers, their fine granularity, and the flexibility of the post divider make the FS714x the most flexible stand-alone phase-locked loop (PLL) clock generator available.
3.0 Applications
SCL SDA ADDR0 VSS XIN XOUT ADDR1 VDD
1 2 3 16 15 14
CLKN CLKP VDD n/c REF VSS n/c IPRG
SCL SDA ADDR0 VSS XIN XOUT ADDR1 VDD
1 2 3
16 15 14
CLKN CLKP VDD SYNC REF VSS n/c IPRG
4 5 6 7 8
13 12 11 10 9
4 5 6 7 8
13 12 11 10 9
* * * *
Precision frequency synthesis Low-frequency clock multiplication Video line-locked clock generation Laser beam printers (FS7145)
Figure 1: Pin Configuration: 16-pin (0.150") SOIC, 16-pin (5.3mm) SSOP
SYNC (FS7145 only) XIN XOUT Crystal Oscillator Reference Divider
(NR)
FS7140 FS7140
FS7145
Sync Control IPRG Loop Filter
REF
PhaseFrequency Detector
UP
Charge Pump
DOWN
Voltage Controlled Oscillator
Post Divider (NPx) CMOS/PECL Output
CLKP CLKN
ADDR[1:0]
Feedback Divider (NF) I2C Interface Registers
SCL SDA
FS7140 / FS7145
Figure 2: Device Block Diagram
AMI Semiconductor www.amis.com
1
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 1: FS7140 Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type DI DIO DID P AI AO DID P AI P DIU P DO DO Name SCL SDA ADDR0 VSS XIN XOUT ADDR1 VDD IPRG n/c VSS REF n/c VDD CLKP CLKN
U
Data Sheet
Description Serial Interface Clock (requires an external pull-up) Serial Interface Data Input/Output (requires an external pull-up) Address Select Bit "0" Ground Crystal Oscillator Feedback Crystal Oscillator Drive Address Select Bit "1" Power Supply (+3.3V nominal) PECL Current Drive Programming No Connection Ground Reference Frequency Input No Connection Power Supply (+3.3V nominal) Clock Output Inverted Clock Output
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
Table 2: FS7145 Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type DI DIO DID P AI AO DID P AI P DIU DIU P DO DO Name SCL SDA ADDR0 VSS XIN XOUT ADDR1 VDD IPRG n/c VSS REF SYNC VDD CLKP CLKN
U
Description Serial Interface Clock (requires an external pull-up) Serial Interface Data Input/Output (requires an external pull-up) Address Select Bit "0" Ground Crystal Oscillator Feedback Crystal Oscillator Drive Address Select Bit "1" Power Supply (+3.3V nominal) PECL Current Drive Programming No Connection Ground Reference Frequency Input Synchronization Input Power Supply (+3.3V nominal) Clock Output Inverted Clock Output
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
AMI Semiconductor www.amis.com
2
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
4.0 Functional Block Description
4.1 Phase Locked Loop (PLL)
The phase locked loop is a standard phase- and frequencylocked loop architecture. The PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider. The reference frequency (generated by either the on-board crystal oscillator or an external frequency source), is first reduced by the Reference Divider. The integer value that the frequency is divided by is called the modulus and is denoted as NR for the reference divider. This divided reference is then fed into the PFD. The VCO frequency is fed back to the PFD through the feedback divider (the modulus is denoted by NF). The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is then:
Data Sheet
modulus. Selected moduli below 12 are also permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not available on date codes prior to 0108). 4.1.3 Post Divider The post divider consists of three individually programmable dividers, as shown in Figure 3.
POST1[3:0]
POST2[3:0]
POST3[1:0]
f VCO
Post Divider 1 (N P1 )
Post Divider 2 (N P2)
POST DIVIDER (N
Px
Post Divider 3 (N P3)
)
fCLK
Figure 3: Post Divider
The moduli of the individual dividers are denoted as NP1, NP2 and NP3, and together they make up the array modulus NPx.
N Px = N P1 N P 2 N P 3
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, the extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. Note that a nominal 50/50 duty factor is always preserved (even for selections which have an odd modulus). See Table 8 for additional information. 4.1.4 Crystal Oscillator The FS7140 is equipped with a Pierce-type crystal oscillator. The crystal is operated in parallel resonant mode. Internal load capacitance is provided for the crystal. While a recommended load capacitance for the crystal is specified, crystals for other standard load capacitances may be used if great precision of the reference frequency (100ppm or less) is not required. 4.1.5 Reference Divider Source MUX The source of frequency for the reference divider can be chosen to be the device crystal oscillator or the REF pin by the REFDSRC bit. When not using the crystal oscillator, it is preferred to connect
fVCO f = REF NF NR
This basic PLL equation can be rewritten as
aeN fVCO = f REF c F cN eR
o / / o
A post-divider (actually a series combination of three post dividers) follows the PLL and the final equation for device output frequency is:
f CLK
aeN = f REF c F cN eR
oae 1 /c /c N oe Px
o / / o
4.1.1 Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of either the crystal oscillator circuit or an external reference frequency. The reference divider is a 12 bit divider, and can be programmed for any modulus from 1 to 4095 (divide by 1 not available on date codes prior to 0108). 4.1.2 Feedback Divider The feedback divider is based on a dual-modulus divider (also called dual-modulus prescaler) technique. It permits division by any integer value between 12 and 16383. Simply program the FBKDIV register with the binary equivalent of the desired
AMI Semiconductor www.amis.com
3
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
XIN to VSS. Do not connect to XOUT. When not using the REF input, it is preferred to leave it floating or connected to VDD. 4.1.6 Feedback Divider Source MUX The source of frequency for the feedback divider may be selected to be either the output of the post divider or the output of the VCO by the FBKDSRC bit. Ordinarily, for frequency synthesis, the output of the VCO is used. Use the output of the post divider only where a deterministic phase relationship between the output clock and reference clock are desired (line-locked mode, for example). 4.1.7 Device Shutdown Two bits are provided to effect shutdown of the device if desired, when it is not active. SHUT1 disables most externally observable device functions. SHUT2 reduces device quiescent current to absolute minimum values. Normally, both bits should be set or cleared together. Serial communications capability is not disabled by either SHUT1 or SHUT2. Then: R1 (from CLKP and CLKN output to VDD) = RLOAD * VDD / VHI = 75 * 3.3 / 2.4 = 103 ohms R2 (from CLKP and CLKN output to GND) = RLOAD * VDD / (VDD - VHI) = 75 * 3.3 / (3.3 - 2.4) = 275 ohms Rprgm (from VDD to IPRG pin) = 26 * (VDD * RLOAD) / (VHI - VLO) / 3 = 26 * (3.3 * 75) / (2.4 - 1.6) / 3 = 2.68 Kohms
Data Sheet
4.3 SYNC Circuitry
The FS7145 supports nearly instantaneous adjustment of the output CLK phase by the SYNC input. Either edge direction of SYNC (positive-going or negative-going) is supported. Example (positive-going SYNC selected): Upon the negative edge of SYNC input, a sequence begins to stop the CLK output. Upon the positive edge, CLK resumes operation, synchronized to the phase of the SYNC input (plus a deterministic delay). This is performed by control of the device post-divider. Phase resolution equal to 1/2 of the VCO period can be achieved (approximately down to 2ns).
4.2 Differential Output Stage
The differential output stage supports both CMOS and pseudoECL (PECL) signals. The desired output interface is chosen via the programming registers. If a PECL interface is used, the transmission line is usually terminated using a Thevenin termination. The output stage can only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of output sink current to IPRG current is 13:1. Source current for the CLKx pins is provided by the pull-up resistors that are part of the Thevenin termination. 4.2.1 Example Assume that it is desired to connect a PECL-type fanout buffer right next to the FS7140. Further assume: * VDD = 3.3V * desired VHI = 2.4V * desired VLO = 1.6V * equivalent RLOAD = 75 ohms
5.0 I2C-bus Control Interface
This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).
AMI Semiconductor www.amis.com
4
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I2C-bus protocol. 5.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 5.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. 5.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 5.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first-overwritten fashion. 5.1.5 Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
Data Sheet
5.2 I2C-bus Operation
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal oscillator does not have to run for communication to occur. The device accepts the following I2C-bus commands: 5.2.1 Slave Address After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is:
A6 1 A5 0 A4 1 A3 1 A2 0 A1 X A0 X
where X is controlled by the logic level at the ADDR pins. The selectable ADDR bits allow four different FS7140 devices to exist on the same bus. Note that every device on an I2C-bus must have a unique address to avoid pos-sible bus conflicts. 5.2.2 Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored. 5.2.3 Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not
AMI Semiconductor www.amis.com
5
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
acknowledge the transfer but does generate a STOP condition. 5.2.4 Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to eight bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a sequential register write. 5.2.5 Sequential Register Read Procedure
Data Sheet
Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all eight bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.
AMI Semiconductor www.amis.com
6
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Data Sheet
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge STOP Condition Acknowledge From device to bus host
Figure 4: Random Register Write Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
AS
DEVICE ADDRESS
RA
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command STOP Condition NO Acknowledge
Figure 5: Random Register Read Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
A
DATA
A
DATA
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device to bus host
Figure 6: Sequential Register Write Procedure
S
DEVICE ADDRESS
WA
REGISTER ADDRESS
AS
DEVICE ADDRESS
RA
DATA
A
DATA
AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command Acknowledge
Data NO Acknowledge STOP Command
Figure 7: Sequential Register Read Procedure
AMI Semiconductor www.amis.com
7
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
6.0 Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written.
Data Sheet
Table 3: FS7140 Register Map ADDRESS BYTE 7 BIT 7 RESERVED
(Bit 63) Must be set to "0"
BIT 6 RESERVED
(Bit 62) Must be set to "0"
BIT 5 RESERVED
(Bit 61) Must be set to "0"
BIT 4 RESERVED
(Bit 60) Must be set to "0"
BIT 3 RESERVED
(Bit 59) Must be set to "0"
BIT 2 RESERVED
(Bit 58) Must be set to "0"
BIT 1 RESERVED
(Bit 57) Must be set to "0"
BIT 0 RESERVED
(Bit 56) Must be set to "0"
RESERVED BYTE 6
(Bit 55) Must be set to "0"
RESERVED
(Bit 54) Must be set to "0"
SHUT2
(Bit 53) 0 = Normal 1 = Powered Down
RESERVED
(Bit 52) Must be set to "0"
RESERVED
(Bit 51) Must be set to "0"
RESERVED
(Bit 50) Must be set to "0"
RESERVED
(Bit 49) Must be set to "0"
RESERVED
(Bit 48) Must be set to "0"
RESERVED BYTE 5
(Bit 47) Must be set to "0"
LC
(Bit 46) Loop Filter Cap Select
LR[1]
(Bit 45)
LR[0]
(Bit 44)
RESERVED
(Bit 43) Must be set to "0"
RESERVED
(Bit 42) Must be set to "0"
CP[1]
(Bit 41)
CP[0]
(Bit 40)
Loop Filter Resistor Select
Charge Pump Current Select
CMOS BYTE 4
(Bit 39) 0 = PECL 1 = CMOS
FBKDSRC
(Bit 38) 0 = VCO Output 1 = Post Divider Output
FBKDIV[13]
(Bit 37) 8192
FBKDIV[12]
(Bit 36) 4096
FBKDIV[11]
(Bit 35) 2048
FBKDIV[10]
(Bit 34) 1024
FBKDIV[9]
(Bit 33) 512
FBKDIV[8]
(Bit 32) 256
See Section 4.1.2 for disallowed FBKDIV values
FBKDIV[7] BYTE 3
(Bit 31) 128
FBKDIV[6]
(Bit 30) 64
FBKDIV[5]
(Bit 29) 32
FBKDIV[4]
(Bit 28) 16
FBKDIV[3]
(Bit 27) 8
FBKDIV[2]
(Bit 26) 4
FBKDIV[1]
(Bit 25) 2
FBKDIV[0]
(Bit 24) 1
See Section 4.1.2 for disallowed FBKDIV values
POST2[3] BYTE 2
(Bit 23)
POST2[2]
(Bit 22)
POST2[1]
(Bit 21)
POST2[0]
(Bit 20)
POST1[3]
(Bit 19)
POST1[2]
(Bit 18)
POST1[1]
(Bit 17)
POST1[0]
(Bit 16)
Modulus = N+1 (N=0 to 11) See Table 8
Modulus = N+1 (N=0 to 11) See Table 8
POST3[1] BYTE 1
(Bit 15)
POST3[0]
(Bit 14)
SHUT1
(Bit 13) 0 = Normal 1 = Powered Down
REFDSRC
(Bit 12) 0 = Crystal Oscillator 1 = REF Pin
REFDIV[11]
(Bit 11) 2048
REFDIV[10]
(Bit 10) 1024
REFDIV[9]
(Bit 9) 512
REFDIV[8]
(Bit 8) 256
Modulus = 1, 2, 4, or 8 See Table 8
REFDIV[7] BYTE 0
(Bit 7) 128
REFDIV[6]
(Bit 6) 64
REFDIV[5]
(Bit 5) 32
REFDIV[4]
(Bit 4) 16
REFDIV[3]
(Bit 3) 8
REFDIV[2]
(Bit 2) 4
REFDIV[1]
(Bit 1) 2
REFDIV[0]
(Bit 0) 1
AMI Semiconductor www.amis.com
8
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 4: FS7145 Register Map ADDRESS BYTE 7 BIT 7 RESERVED
(Bit 63) Must be set to "0"
Data Sheet
BIT 6 RESERVED
(Bit 62) Must be set to "0"
BIT 5 RESERVED
(Bit 61) Must be set to "0"
BIT 4 RESERVED
(Bit 60) Must be set to "0"
BIT 3 RESERVED
(Bit 59) Must be set to "0"
BIT 2 RESERVED
(Bit 58) Must be set to "0"
BIT 1 RESERVED
(Bit 57) Must be set to "0"
BIT 0 RESERVED
(Bit 56) Must be set to "0"
RESERVED BYTE 6
(Bit 55) Must be set to "0"
RESERVED
(Bit 54) Must be set to "0"
SHUT2
(Bit 53) 0 = Normal 1 = Powered Down
RESERVED
(Bit 52) Must be set to "0"
RESERVED
(Bit 51) Must be set to "0"
RESERVED
(Bit 50) Must be set to "0"
SYNCPOL
(Bit 49) "0" = negative "1" = positive
SYNCEN
(Bit 48) "0" = negative "1" = positive
RESERVED BYTE 5
(Bit 47) Must be set to "0"
LC
(Bit 46) Loop Filter Cap Select
LR[1]
(Bit 45)
LR[0]
(Bit 44)
RESERVED
(Bit 43) Must be set to "0"
RESERVED
(Bit 42) Must be set to "0"
CP[1]
(Bit 41)
CP[0]
(Bit 40)
Loop Filter Resistor Select
Charge Pump Current Select
CMOS BYTE 4
(Bit 39) 0 = PECL 1 = CMOS
FBKDSRC
(Bit 38) 0 = VCO Output 1 = Post Divider Output
FBKDIV[13]
(Bit 37) 8192
FBKDIV[12]
(Bit 36) 4096
FBKDIV[11]
(Bit 35) 2048
FBKDIV[10]
(Bit 34) 1024
FBKDIV[9]
(Bit 33) 512
FBKDIV[8]
(Bit 32) 256
See Section 4.1.2 for disallowed FBKDIV values
FBKDIV[7] BYTE 3
(Bit 31) 128
FBKDIV[6]
(Bit 30) 64
FBKDIV[5]
(Bit 29) 32
FBKDIV[4]
(Bit 28) 16
FBKDIV[3]
(Bit 27) 8
FBKDIV[2]
(Bit 26) 4
FBKDIV[1]
(Bit 25) 2
FBKDIV[0]
(Bit 24) 1
See Section 4.1.2 for disallowed FBKDIV values
POST2[3] BYTE 2
(Bit 23)
POST2[2]
(Bit 22)
POST2[1]
(Bit 21)
POST2[0]
(Bit 20)
POST1[3]
(Bit 19)
POST1[2]
(Bit 18)
POST1[1]
(Bit 17)
POST1[0]
(Bit 16)
Modulus = N+1 (N=0 to 11) See Table 8
Modulus = N+1 (N=0 to 11) See Table 8
POST3[1] BYTE 1
(Bit 15)
POST3[0]
(Bit 14)
SHUT1
(Bit 13) 0 = Normal 1 = Powered Down
REFDSRC
(Bit 12) 0 = Crystal Oscillator 1 = REF Pin
REFDIV[11]
(Bit 11) 2048
REFDIV[10]
(Bit 10) 1024
REFDIV[9]
(Bit 9) 512
REFDIV[8]
(Bit 8) 256
Modulus = 1, 2, 4, or 8 See Table 8
REFDIV[7] BYTE 0
(Bit 7) 128
REFDIV[6]
(Bit 6) 64
REFDIV[5]
(Bit 5) 32
REFDIV[4]
(Bit 4) 16
REFDIV[3]
(Bit 3) 8
REFDIV[2]
(Bit 2) 4
REFDIV[1]
(Bit 1) 2
REFDIV[0]
(Bit 0) 1
AMI Semiconductor www.amis.com
9
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 5: Device Configuration Bits Name REFDSRC FBKDSRC SHUT1 SHUT2 CMOS Description REFerence Divider SouRCe [0] = Crystal Oscillator / [1] = REF Pin FeedB ack Divider SouRCe [0] = VCO Output / [1] = Post Divider Output SHUTdown1 [0] = Normal / [1] = Powered Down SHUTdown2 [0] = Normal / [1] = Powered Down CLKP/CLKN Output Mode [0] = PECL Output / [1] CMOS Output Table 9: Post Divider Control Bits Name Description POST Divider #1 (NP1) Modulus [0000] 1 [0001] 2 [0010] 3 [0011] 4 [0100] 5 [0101] 6 [0110] 7 [0111] 8 [1000] 9 [1001] 10 [1010] 11 [1011] 12 [1100] [1101] Do not use [1110] [1111] POST Divider #2 (NP2) Modulus [0000] 1 [0001] 2 [0010] 3 [0011] 4 [0100] 5 [0101] 6 [0110] 7 [0111] 8 [1000] 9 [1001] 10 [1010] 11 [1011] 12 [1100] [1101] Do not use [1110] [1111] POST Divider #3 (NP3) Modulus [00] 1 [01] 2 [10] 4 [11] 8
Data Sheet
POST1[3:0]
Table 6: Main Loop Tuning Bits Name Description Charge Pump Current [00] [01] [10] [11] Loop Filter Resistor Select [00] [01] [10] [11] Loop Filter Capacitor Select [0] [1]
CP[1:0]
2.0mA 4.5mA 11.0mA 22.5mA 400KW 133KW 30KW 12KW 185pF 500pF POST2[3:0]
LR[1:0]
LC
Table 7: PLL Divider Control Bits NAME REFDIV[11:0] FBKDIV[13:0] DESCRIPTION REFerence DIVider (NR) FeedBacK DIVider (NR)
Table 8: SYNC Control Bits (FS7145 only) Name SYNCEN SYNCPOL Description SYNC Enable [0] = Disabled / [1] = Enabled SYNC POLarity [0] = Negative Edge / [1] = Positive Edge
POST3[1:0]
AMI Semiconductor www.amis.com
10
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
7.0 Electrical Specifications
Table 10: Absolute Maximum Ratings Parameter Supply Voltage, dc (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Reflow Solder Profile Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 Symbol VDD V1 VO IIK IOK TS TA TJ Min. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 Max. 4.5 VDD+0.5 VDD+0.5 50 50 150 125 150 Units V V V mA mA C C C Per IPC/JEDEC J-STD-020B kV
Data Sheet
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 11: Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Symbol VDD TA Conditions/Description Min. 3.0 0 Typ. 3.3 Max. 3.6 70 Units V C
AMI Semiconductor www.amis.com
11
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 12: DC Electrical Specifications Parameter Overall Supply Current, Dynamic Supply Current, Static Serial Communication I/O (SDA, SCL) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current Low-Level Output Sink Current (SDA) Address Select Input (ADDR0, ADDR1) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (pull-down) Low-Level Input Current Reference Frequency Input (REF) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-down) Sync Control Input (SYNC) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-down) Crystal Oscillator Input (XIN) Threshold Bias Voltage High-Level Input Current Low-Level input Current Crystal Frequency Crystal Oscillator Output (XOUT) High-Level Output Source Current Low-Level Output Sink Current PECL Current Program I/O (IPRG) Low-Level Input Current Clock Outputs, CMOS Mode (CLKN, CLKP) High-Level Output Source Current Low-Level Output Sink Current Clock Outputs, PECL Mode (CLKN, CLKP) IPRG Bias Voltage IPRG Bias Current Sink Current to IPRG Current Ratio Tristate Output Current IZ -10 VIPRG IIPRG VIPRG will be clamped to this level when a resistor is connected from VDD to IPRG IIPRG - (VVDD - VIPRG) / RSET VDD/3 3.5 13 10 mA V IOH IOL VO = 2.0V VO = 0.4V 19 -35 IIL VIPRG = 0V; PECL Mode -10 10 mA IOH IOL VXOUT = 0 VXOUT = VDD -8.5 11 VTH IIH IIL FX VXIN = VDD VXIN = GND Fundamental mode For best matching with internal crystal oscillator load 16-18 VDD/2 40 -40 35 V mA mA VIH VIL IIH IIL VREF = VDD VREF = 0V -1 -30 VVDD-1.0 0.8 1 V V mA mA VIH VIL IIH IIL VREF = VDD VREF = 0V -1 -30 VVDD-1.0 0.8 1 V V mA mA VIH VIL IIH IIL VADDRx = VDD VADDRx = 0V -1 30 1 VVDD-1.0 0.8 V V mA mA VIH VIL Vhys II IOL SDA, SCL in read condition SDA in acknowledge condition; VSDA = 0.4V -10 5 14 0.33*VDD +10 0.8*VDD V 0.2*VDD V V mA IDD IDDL CMOS mode; FXTAL = 15MHz; FVCO = 400MHz; FCLK = 200MHx; does not include load current SHUT1, SHUT2 bit both "1" 35 400 700 Symbol Conditions/Description Min. Typ. Max.
Data Sheet
Units
mA mA
mA
MHz pF mA mA
Recommended Crystal Load Capacitance* CL(XTAL)
mA mA
mA
Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are 3s from typical. Negative currents indicate current flows out of the device.
AMI Semiconductor www.amis.com
12
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 13: AC Timing Specifications Parameter Overall Output Frequency* VCO Frequency* CMOS Mode Rise Time* CMOS Mode Fall Time* PECL Mode Rise Time* PECL Mode Fall Time* Reference Frequency Input (REF) Input Frequency Reference High Time Reference Low Time Sync Control Input (SYNC) Sync High Time Sync Low Time Clock Output (CLKP, CLKN) Duty Cycle (CMOS Mode)* Duty Cycle (PECL Mode)* Measured at 1.4V Measured at zero crossings of (VCLKP-VCLKN) 50 50 tSYNCH tSYNCL for orderly CLK stop/start for orderly CLK stop/start 3 3 FREF tREHF tREFL 3 3 80 fO(max) fVCO tr tf tr tf CL = 7pF CL = 7pF CL = 7pF; RL = 65 ohm CL = 7pF; RL = 65 ohm CMOS outputs PECL outputs 0 0 40 1 1 1 1 150 300 400 Symbol Conditions/Description Clock (MHz) Min. Typ. Max.
Data Sheet
Units
MHz MHz ns ns ns ns MHz ns ns TCLK TCLK % % ps ps ps ps ps ps ps ps ps
For valid programming solutions. Long-term (or cumulative) jitter specified is RMS position error of any edge compared with an ideal clock generated from the same reference frequency. It is measured with a time interval analyzer using a 500 microsecond window, using statistics gathered over 1000 samples. Jitter, Long Term (sg(t))* tj(LT) FREF/NREF > 1000kHz FREF/NREF ~= 500kHz FREF/NREF ~= 250kHz FREF/NREF ~= 125kHz FREF/NREF ~= 62.5kHz FREF/NREF ~= 31.5kHz Jitter, Period (peak-peak)* tj(DP) 40MHz < VCO Frequency < 100MHz VCO Frequency > 100MHz 25 50 100 190 240 300 75 50
Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are 3s from typical.
Table 14: Serial Interface Timing Specifications Parameter Clock Frequency Bus Free Time Between STOP and START Setup Time, START (repeated) Hold Time, START Setup Time, Data Input Hold Time, Data Input Output Data Valid From Clock Rise Time, Data and Clock Fall Time, Data and Clock High Time, Clock Low Time, Clock Setupt Time, STOP Symbol fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tAA tR tF tHI tLO tsu:STO SDA, SCL SDA, SCL SCL SCL 600 1300 600 SDA SDA Conditions/Description SCL Fast Mode Min. 0 1300 600 600 100 0 900 300 300 Max. 400 Units kHz ns ns ns ns ns ns ns ns ns ns ns
Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are 3s from typical.
AMI Semiconductor www.amis.com
13
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Data Sheet
~ ~
SCL
tsu:STA thd:STA tsu:STO
~ ~
SDA
~ ~
START
ADDRESS OR DATA VALID
DATA CAN CHANGE
STOP
Figure 8: Bus Timing Data
tF
tHI
tR
~ ~
SCL
tLO tsu:STA thd:STA thd:DAT
tsu:DAT
tsu:STO
~ ~
SDA IN
tAA tAA
tBUF
~ ~
SDA OUT
Figure 9: Data Transfer Sequence
8.0 Package Information for `Green' (FS7140) and `Non-Green' (FS7140 & FS7145)
Table 15: 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Min. A A1 A2 B C D E e H h L Q 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 0 Max. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 8 Millimeters Min. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 0 Max. 1.73 0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89 8
BASE PLANE 1 ALL RADII: 0.005" TO 0.01"
16
E
H
B
e A2 D A1
SEATING PLANE
h x 45
7 typ.
0.050 BSC
1.27 BSC
A
C L q
AMI Semiconductor www.amis.com
14
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 16: 16-pin SOIC (0.150") Package Characteristics Parameter Thermal Impedance, Junction to Free-Air Lead Inductance, Self Symbol QJA L11 Conditions/Description Air flow = 0 ft./min. Corner lead Center lead Typ. 108 2.5 1.2 Units CW nH nH
Data Sheet
Table 17: 16-pin 5.3mm (0.209") SSOP Package Dimensions
16
Dimensions Inches Min. A A1 A2 B C D E e H L Q 0.068 0.002 0.066 0.010 0.005 0.239 0.205 0.301 0.022 0 Max. 0.078 0.008 0.070 0.015 0.008 0.249 0.212 0.311 0.037 8 Millimeters Min. 1.73 0.05 1.68 0.25 0.13 6.07 5.20 7.65 0.55 0 Max. 1.99 0.21 1.78 0.38 0.20 6.33 5.38 7.90 0.95 8
E
H
1
B
e A2 D A1
SEATING PLANE
0.0256 BSC
0.65 BSC
A
C L q
BASE PLANE
Table 18: 16-pin 5.3mm (0.208") SSOP Package Characteristics Parameter Thermal Impedance, Junction to Free-Air 16-pin 0.150" SOIC Lead Inductance, Self Symbol QJA L11 Conditions/Description Air flow = 0ms Corner lead Center lead TYP. 90 2.3 1 UNITS C/W nH nH
9.0 Ordering Information
Ordering Code 13715-802 13715-201 13715-102 13715-202 13715-805 Device Number FS7140-01 FS7140-01 FS7145 FS7145 FS7140-01g Package Type 16-pin (0.150") SOIC 16-pin (5.3mm) SSOP 16-pin (0.150") SOIC 16-pin (5.3mm) SSOP 16-pin (5.3mm) SSOP `green' or lead-free packaging Operating Temperature Range 0C to 70C (commercial) 0C to 70C (commercial) 0C to 70C (commercial) 0C to 70C (commercial) 0C to 70C (commercial) Shipping Configuration Tape and reel/tubes (please specify) Tape and reel/tubes (please specify) Tape and reel/tubes (please specify) Tape and reel/tubes (please specify) Tape and reel/tubes (please specify)
AMI Semiconductor www.amis.com
15
(c) 2004 AMI Semiconductor, Inc. AMI Semiconductor makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty contained in AMI Semiconductor's Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of AMI Semiconductor are granted by the company in connection with the sale of AMI Semiconductor products, expressly or by implication. I2C is a licensed trademark of Philips Electronics, N.V. AMI Semiconductor reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. IM

▲Up To Search▲

Price & Availability of FS7145

	To Download FS7145 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .